Elphel Development Blog

10373A – new functionality added

It seems that those additional parts did fit on the board. I still need to restore some power connections and the legend on the board (it is also getting to be a real challenge – the smallest letters have to use 0.125mm (5 mil) lines and there is very little space between the components. It will need some time, but it is definitely doable. This is how the board looks now (click on the image to get the full size):

So to the 10373 features I listed initially in my May, 18 post:

• TMS320DM6467 as the CPU
• Xilinx Spartan 6 FPGA
• 256 MiB NAND flash
• 256 MiB DDR2 system memory
• 256 MiB DDR3 dedicated FPGA memory
• 48V DC over Ethernet cable
• GigE
• USB 2.0 host
• ATA port (to be used with the SATA bridge on the 10369 or similar I/O board)
• USB 1.1 device with micro USB connector. It is connected to the CPU serial port to be used as a system console and alternative boot source

Few more can be added:

• Two sensor ports, each can accommodate existent sensor front ends that work with NC353L cameras. Both sensors will be able to operate at full resolution/speed in parallel.
• SATA port with the flex cable connector. The connector pinout is made so it is possible to use flexible cables (single-layer) , not just 2-layer cable or flex PCB to achieve 100 Ohm impedance for the high-speed differential pairs. On the other end of that cable there will be either eSATA connector on the back panel of the camera or an adapter for the 64GB SSD used in some EEE PC computers. As you can see on Elphel wiki these 64GB memory can easily fit inside the camera – so no more CF cards. Same with 1.8″ HDD – we can make an adapter from the same flex cable – it addition to SATA signals it has both 3.3VDC and 5VDC power.
• Another flex cable connector has USB 2.0 (host) signals, including 5V power and additional 3.3V and 4 GPIO signals from the FPGA. It is possible to put just micro USB connector adapter on the camera back panel (it is likely to be combined with the eSATA one to simplify mounting) or have a 4-port USB hub (similar to the one in the 10369 board) and additional flex-cable connectors for internal USB or I2C internal add-ons (i.e compass).
• Clock/calendar with a super-capacitor power backup, similar to the one in our current 10369A board, but with the additional function – 10373 makes use of the alarm of that clock (it can be set up to a week in the future). Alarm output is used to re-power the camera after it turned itself off (and it can now). DC-DC converters still consume several mA when turned off, but it will be possible to use the camera with a very small solar panel in the wilderness unattended – either periodically recording images to the internal memory or using USB cellular module (if the area has coverage) to upload the images.

And here is where I’m working on this board – 110.965W 40.65168N. It is raining most of the time – day and night, so I have more time to work.

10373 – working on the PCB layout 2

After finishing the 10373 layout I did not feel satisfied – some valuable parts of the PCB were left wasted. When I was just starting this project I new I’ll have to use more layers (now 8, previous designs – 4), smaller traces (0.075 mm – down from 0.1mm) and use buried and blind vias that I never did before. And I still was not sure if everything will fit on the same board size, I even had a plan B for the system memory – use just one x16 chip and have lower bandwidth, but both chips did fit nicely (they are visible as large vertical rectangles just above the center of the board). And when I just started placement, I noticed that several hundred of  huge 0402 resistors and capacitors will not actually fit around the chip with 0.4mm distnace between the pads. Each such resitor is longer than a millimiter, so I changed most of them (few do not exist in small package) to 0201 – that was better, just 0.6mm by 0.3mm. End everything did fit and some extra remained so I’m trying to put more of the useful components.

So I broke the layout, renamed the board to rev “A” (even as rev “0” was never build) and added few more connectors, ICs and other components and now I’m working on making the increased number of parts fit (some are still around the board, not yet placed). That huge supercapaitor on top (used for clock/calendar backup instead of a battery) will be placed over other components so it does not need that much empty space.

It will take me some time to fit everything, but it seems to be possible. And then the board will be really packed with no space wasted. And camera board – get more functionality even when no extension board will be installed.
Andrey

There will be two sensor ports on the 10373 board

After finishing the PCB layout of the 10373 board I noticed that it is very easy to add a second sensor board connector.

First of all – there is room for that connector – space wasted between the two tabs with mounting holes that we added at the request of our customer. And the connector nicely fits there.

Then – the bank 0 of the Spartan 6 FPGA has enough pins for 2 sensor ports (each port uses 22 I/O lines).

The 10373 board is expected to have 3-4 times higher processing speed than 10353 so using it with the current sensor boards would keep it under-loaded. For the newer (and faster) sensors I plan to use high speed serial transceivers of the Spartan chips as I wrote earlier, but the first revision will be compatible with the older sensors.

That second connector would cost just the price of the connector as I use free so far space on the board and unused pins on the FPGA. It can be used in multiple ways, such as:

1 – stereo cameras. It will be possible to incorporate code Oleg is working on now for automatic processing of the 3-d information – i.e. for autonomous vehicles. And having higher bandwidth of the system and network it will be possible to stream or record both of the stereo channels at the full resolution/frame rate sensor is capable of – it could be used for stereo cinema applications.

2 – panoramic applications with fewer number of complete camera modules, fewer network ports than needed currently when the 353 cameras are used.

3 – Day/night cameras with both color (with IR cutoff filter) and monochrome (without filter) sensors connected at the same time.

Andrey

Now it looks like this:

work updates

1. [Done] Finish with the “full_pages_in_buffer“. Made more convenient to me and corrected the error I had done before (double write request from channel).

2. [In Progress] Verification of everything.

Currently instead of black frames I get different ones (apparently, something’s wrong: black vertical lines after each 1024 pixels) – checking the simulation:

Fig. 1 Test image, size 2592×1940

TODO:

1. Verification.

2. I also didn’t implemented multiplication on the Hamming function before performing the FFTs.

10373 – working on the PCB layout

I do not know why search engines love this 8-year old page – current camera model is 393. It’s PCB layout is also available in both Gerber and PDF form on this wiki page.

I’m working now on the 10373 PCB layout – there will be some minor cleanup and double-checking all the new components used, their mechanical dimensions and pinouts, but so far I was able to fit all the components to the same size PCB and route all the traces. Sure I had to use more layers – there are 8 now, including 4 dedicated to ground and power planes, there are now blind laser microvias between the the outer layers and the next ones, some buried vias and reduced traces widths.

And there is even some room left on the board – something to be added later in the next revision.

Andrey

work report

1. [Done] Simulation of data path of Cross-Correlation (C-C) module.

2. [Done] Integration of the C-C block to x359.

3. [In Progress] Simulation of the C-C and x359 as a whole.

3.a. [Done] Set up memory controller.

• Write length is set to 64(8×8) words.
• Fixed image size to 2592×1944.
• C-C block is set to work with 512 words, reading out 256 word at a time with overlapping – 3 256-word reads till another command to the C-C block.

3.b. [Done] Simulate for 1 write and 1 read channels. Here there are no competetive requests from 2 write channels.

3.c. [In Progress] Simulate for 2 write and 2 read channels.

• Fixed reg “full_pages_in_buffer” correct work. It was commented earlier by me as I used only one channel at a time to access SDRAM.

• For write channels – changed reg “full_pages_in_buffer” size to 32 (page size is 64). And if it reaches the maximum then a aditional BRAM is neaded.

TODO:

1. Finish with the “full_pages_in_buffer“.

2. Make an x359.bit and check the work with the whole frame.

3. I also didn’t implemented multiplication on the Hamming function before performing the FFTs.

Circuit design – 10373

It seems I finished the first pass of the 10373 circuit design – “first pass” as the design is likely to change somewhat during PCB layout stage. The challenging part turned out to be power management – TI DaVinci (at least in it’s current version as TMS320DM6467) is rather power-hungry, needs significantly more of it than the Axis ETRAX FS that was used in the NC353L camera, even as it it smaller in size  – and I’m really anxious to fit more stuff on the same size PCB as in the older cameras.

Sure enough that extra electrical power gives more badly needed computational power too and I wanted to have universal system board that can use the extra power when available but be able to survive (scaling down performance) when used in mobile applications. And I believe I did balance it properly and hope to make it through the PCB layout and fit increased number of components, but four layer PCB of the 303-313-323-333-353 cameras will have to go – number of layers will go up to (most likely) eight.

It may be a tradition or superstition – I am not going to post the circuit diagram until the hardware will be built and tested.  So far I can only list some of the features of the 10373 system board:

• TMS320DM6467 as the CPU
• Xilinx Spartan 6 FPGA
• 256 MiB NAND flash
• 256 MiB DDR2 system memory
• 256 MiB DDR3 dedicated FPGA memory
• 48V DC
• GigE
• USB 2.0 host
• ATA port (to be used with the SATA bridge on the 10369 or similar  I/O board)
• USB 1.1 device with micro USB connector. It is connected to the CPU serial port to be used as a system console and alternative boot source

FFT256 DIF

1. [Done] Wrote code for the FFT256 DIF.

• Resources

FFT is performed in 8 conveyor organized stages. Each stage is similar to as described here. So far each stage uses 2 BRAM ports (A for 16-bit Re-part and B for 16-bit Im-part) and the 1 MULT18X18 (for the “butterfly”) – 4 BRAMs + 6 MULT18X18s (MULTs are not used in the last 2 stages). Plus other logic – 1 FFT256 uses 18% of FPGA resourses.

• Performance time

Each BRAM is shared by 2 stages for write and by 2 stages for read (e.g., write – stages 2,3 and read – stages 3,4) – and because the address bus is used for 4 double accesses then each channel double writes/reads every 8 tacts – this results in:

Load time + Computation time + Readout time @10ns Clk ~ 2.5us + 8×10us + 2.5us = 85us =(

1a. [Done] Removed 2 MULTs from the stages 7 & 8 – because the sine and cosine are +/-1 or 0 – no need in multiplication.

2. [In Progress] FFT256 verification – calculated coefficients in OOo Spreadsheet – for tested sequence the results are almost equal – will be better to move it to the testbench.

TODO: (almost the same because initially there was a DIT algorithm and I was writing DIF)

1. Write a correlation computation block.
2. Make FFT run faster – get away from full buffering between stages.
   
3. Set up memory controller for frames read/write.
4. Integrate the correlation block to 10359’s firmware.

FFT256

1. [Done] Add headers and commit to CVS.

2. [Done] Optimize BRAM usage.

4 BRAMs & 8 MULTs, ~150MHz after Synthesis (will be less of course after implementation)

Fig.1 FFT256 diagram

3. [In Progress] FFT256 Verification.

NOTES:

• Do wires to BRAM36X36 and to MULT18X18 are shared? Can I use all 28 BRAMs and 28 MULTs in one design?

TODO:

1. Check if the FFT256 results are correct.
2. Write a correlation computation block.
   1. Write complex multiplication of 2 FFT256s (in order to get a cross-correlation spectrum)
   2. Add IFFT256 run for the multiplication result.